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Placement of Components
The FAN7392 has a negative V S transient performance
curve, as shown in Figure 38.
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-10
The recommended placement and selection of compo-
nent as follows:
? Place a bypass capacitor between the V DD and V SS
pins. A ceramic 1μF capacitor is suitable for most
applications. This component should be placed as
close as possible to the pins to reduce parasitic ele-
ments.
? The bypass capacitor from V CC to COM supports both
the low-side driver and bootstrap capacitor recharge.
A value at least ten times higher than the bootstrap
capacitor is recommended.
? The bootstrap resistor, R BOOT , must be considered in
sizing the bootstrap resistance and the current devel-
oped during initial bootstrap charge. If the resistor is
needed in series with the bootstrap diode, verify that
V B does not fall below COM (ground). Recommended
use is typically 5 ~ 10 ? that increase the V BS time
constant. If the votage drop of of bootstrap resistor
and diode is too high or the circuit topology does not
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0
100
200
300
400 500 600
Pulse Width [ns]
700
800
900 1000
allow a sufficient charging time, a fast recovery or
ultra-fast recovery diode can be used.
? The bootstrap capacitor, C BOOT , uses a low-ESR
Figure 38. Negative V S Transient Chracteristic
Even though the FAN7392 has been shown able to han-
dle these negative V S tranient conditions, it is strongly
recommended that the circuit designer limit the negative
V S transient as much as possible by careful PCB layout
to minimized the value of parasitic elements and compo-
nent use. The amplitude of negative V S voltage is pro-
portional to the parasitic inductances and the turn-off
speed, di/dt, of the switching device.
General Guidelines
Printed Circuit Board Layout
The relayout recommended for minimized parasitic ele-
ments is as follows:
? Direct tracks between switches with no loops or devia-
tion.
? Avoid interconnect links. These can add significant
inductance.
? Reduce the effect of lead-inductance by lowering
package height above the PCB.
? Consider co-locating both power switches to reduce
track length.
? To minimize noise coupling, the ground plane should
not be placed under or near the high-voltage floating
side.
? To reduce the EM coupling and improve the power
switch turn-on/off performance, the gate drive loops
must be reduced as much as possible.
? 2009 Fairchild Semiconductor Corporation
FAN7392 Rev. 1.0.4
15
capacitor, such as ceramic capacitor.
It is stongly recommended that the placement of compo-
nents is as follows:
? Place components tied to the floating voltage pins (V B
and V S ) near the respective high-voltage portions of
the device and the FAN7392. NC (not connected) pins
in this package maximize the distance between the
high-voltage and low-voltage pins ( see Figure 5 ).
? Place and route for bypass capacitors and gate resis-
tors as close as possible to gate drive IC.
? Locate the bootstrap diode, D BOOT , as close as possi-
ble to bootstrap capacitor, C BOOT .
? The bootstrap diode must use a lower forward voltage
drop and minimal switching time as soon as possible
for fast recovery or ultra-fast diode.
www.fairchildsemi.com
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